Accurate and affordable packet-train testing systems for multi-Gb/s networks

Communication networks face nowadays a relentless increase in traffic load. Multi-Gb/s links are becoming widespread, and network devices are under a continuous stress, so testing whether they guarantee the specified throughput or delay is a must. Software-based solutions, such as the packet-train traffic injection, were adequate for lower speeds, but they have turned inaccurate in the current scenario. Hardware-based solutions have proved to be very accurate, but usually at the expense of much higher development and acquisition costs. Fortunately, the new affordable FPGA SoC devices, as well as highlevel synthesis tools, can very efficiently reduce these costs. In this paper we show the advantages of hardware-based solutions in terms of accuracy, comparing the results obtained in an FPGA SoC development platform and in NetFPGA-10G to those of software. Results show that a hardware-based solution is significantly better, especially at 10 Gb/s. By leveraging high-level synthesis and open source platforms, prototypes were quickly developed. Noticeable advantages of our proposal are the high accuracy, the competitive cost with respect to the software counterpart, which runs in high-end off-the-shelf workstations, and the capability to easily evolve to upcoming 40 Gb/s and 100 Gb/s networks.